Semiconductor substrates, and in particular, substrates that include processors and processing systems, continue to operate at increasing faster data rates leading to higher current consumption levels. In some cases, the frequency of operation may be set by the lower limit of the voltage in the voltage tolerance window. The smaller the voltage tolerance window around the nominal operating voltage, the higher the supply voltage must be to achieve a higher operating frequency and hence, higher data rates. One goal of package design is to help reduce the voltage tolerance window around the nominal operating voltage. Adding capacitance between ground (Vss) and supply (Vcc) power planes in a package helps reduce the voltage tolerance window allowing, in the case of processor and processing systems, higher operating frequencies.
Convention approaches to providing capacitance between the power planes utilize a parallel plate structure formed by the power planes with dielectric between the plates. Design criteria for a particular technology limits the maximum capacitance available in these conventional approaches. This capacitance is often insufficient for operating high frequency processors and processing systems.
Thus there is a general need for a package structure with increased capacitance. There is also a need for a package structure suitable for use with high frequency processors and processor systems. There is also a need for a package structure with increased capacitance that falls within design criteria for a particular technology.